The firmware running on Althea/RAFFERTY https://github.com/mzandrew/hdl/blob/master/verilog/src/mza-test032.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.v takes a 508.8875 MHz clock input, and uses a PLL to generate 4 phases of a 127.221875 MHz clock (input/4).  Then it uses a 4-bit iserdes on the input clock to register the phase of the revolution marker on the output clock.  It takes about 1 second worth of these and populates a histogram.  Then it uses the most popular choice and outputs the corresponding phase of the 127 MHz so that the boardstack gets a revolution marker on that 127 MHz clock and the "bunch-0" happens during the first quarter of whichever 127 MHz clock the boardstack sees.  This scheme *should* avoid having bunch-0 show up in a different quarter of the 127 MHz clock upon every power cycle.

The measured difference between revolution marker in from accelerator to revolution marker out to boardstack is 93.64 ns.  This is measured on Althea/RAFFERTY in the D8 HER optics hut, but should be similar when in the tunnel because Althea/RAFFERTY has since been moved down there and the cable lengths after that are on the order of ~1 m.  Overall delay from the accelerator revolution marker (in optics hut) to what Althea/RAFFERTY gets is still yet to be measured (and moreover what the phase of that is to when the synchrotron radiation from "bunch-0" goes through the HER He box).