SuperKEKB XRM system, Page 1 of 2  Not logged in ELOG logo
ID Date Author Type Subject Text Attachments
  1   Tue Apr 19 19:09:25 2016 James BynesInstructionsObtaining data from XRM development boardstackHere are the instructions to obtain data from
XRM boardstack. This has currently been tested
with 1 carrier board, but little modifications
 XRMdataExtractor.c 
  2   Sun May 1 01:45:45 2016 James BynesInstructionsSetting up Ubuntu 14.04 to take data from XRM boardstackThis ELOG shows how to obtain data from XRM
boardstack from a fresh install of Ubuntu
14.04
 XRMdataExtractor.c 
  3   Tue May 3 08:11:06 2016 M. Andrewdocumentationwhat was done in January 2016Here is a data dump of everything that
happened on the asus laptop while getting
the laste 2015 / early 2016 incarnation of
 19x 
  4   Sat May 7 20:52:24 2016 James Bynes IIIInstructionsPlotting data from XRM boardstack
[SIZE=3]The following package will allow
you to parse binary data from TargetX and
 XRMdataExtractor.tar.gz 
  5   Tue May 17 16:03:12 2016 Gary Varnerreportcompilation logFollowing up on James` suggestion, have
posted transcript of compilation log below.

Not sure if there is anything should
 compile.txt 
  6   Wed May 18 01:13:55 2016 Chris Ketter, Gary Varneranalysisfirst data setsAfter getting data logging earlier in the
day, Chris installed the detector and we
took a look at data.
 6x 
  7   Wed May 18 21:32:21 2016 Gary Varnernoise during RF conditioning(?)carrier 0, asic 0There is bursts of noise seen in the longer
record lengths (1).

Some channels are quieter (2),
 ch4_RFon.pngch4_RFon_4k.pngch4_RFon_zoom.pngch7_RFon_zoom.png 
  8   Thu May 19 02:08:09 2016 Gary Varneranalysisstatistics during RF on runSummary statistics for short [1 run @ 64
windows] (1) and longer [100x] (2) show rather
similar responses, where channels 6&7
 RFon_noiseSummary.pngRFon_noiseSummary.gifInterleaveCMdiff.png2-0_CMdiff.png 
  9   Thu May 19 13:49:23 2016 Gary Varnerdata taking problem reportmorning 20-MAY-2016 JSTAfter beam came back on overnight, wanted
to get a background reference data set.

However when trying to log data
  
  10   Thu May 19 19:48:14 2016 John Flanagan, Gary Varnernetwork documentationAPC network configuration
host name  : psxrd08
IP address :
172.19.62.89
MAC address: 00:c0:b7:b8:94:f9





> SuperKEKB ネットワーク
  
  11   Thu May 19 23:01:35 2016 Gary Varneranalysisfirst tryStarted a 1Hz run and let it run, the tail
end of which might have had the detector
in the xray beam.
 ch0_timeseries.pngch0_logPeds.png 
  12   Fri May 20 16:08:46 2016 John Flanagan, Gary Varnerhardware documentationAPC and PDU AC-power settingsControlling remotely via separate laptop,
with connections on the 2 subnets .0 
and  .1
  
  13   Fri May 20 23:30:23 2016 Chris KetterinformationConfiguration of XRMAttachment 1 is a block diagram of
the XRM setup for the Low Energy Ring (LER).
Physically, this is located underneath the
 XRM_connection_diagram.pngXRM_detector.pngXray_beamline.pngXray_source.png 
  14   Sat May 21 01:02:13 2016 John Flanagan, Gary Varnerrun reportFirst Light!After a battle to sort out the networking
issues with the APC (on loan) and PDU, able
to get all working fine, and logged in separate
 firstLight_ch0.pdffirstSamples.png 
  15   Tue Jan 22 07:56:56 2019 M. Andrewdocumentationinstructions for setup, compiling and data acquisitionFile XRM.instructions.txt
gives the 2019-era details on running the
XRM.
 XRM.instructions.txt 
  16   Tue Jun 18 11:29:30 2019 M. Andrewdocumentationraspberry pito install:


cd
mkdir -p build
  
  17   Mon Sep 30 09:36:16 2019 M. Andrewdocumentationmeasurements of accelerator clock and revolution markerFollowing Nuclear Instruments and Methods
in Physics Research A 499 (2003) 138–166,
we know that the distributed accelerator
 superkekb-accelerator-clock-frequency.pngsuperkekb-revolution-marker-frequency.pngdelay-stability-of-accelerator-clock-edge-to-revolution-marker-edge.png 
  18   Mon Sep 30 10:59:35 2019 M. AndrewdocumentationAlthea/RAFFERTYThe firmware running on Althea/RAFFERTY
https://github.com/mzandrew/hdl/blob/master/verilog/src/mza-test032.pll_509divider_and_revo_encoder_plus_calibration_serdes.althea.v
takes a 508.8875 MHz clock input, and uses
 delay-from-revolution-marker-in-to-revo-out-to-boardstack.png 
  19   Fri Oct 4 08:55:23 2019 M. Andrewdocumentationinstructions for pdu controlControl of the power distribution unit (pdu)
is done from xrd04rp2.  The script pdu.sh
is in the $PATH.
  
  20   Fri Oct 4 10:04:12 2019 M. Andrewdocumentationinstructions for programming boardstackProgramming the boardstack is done from xrd04rp2.
 The script boardstack.sh is in the $PATH.
  
ELOG V3.1.5-3a5f2f0